Copyright © 2010 by Wayne Stegall
Updated September 2, 2010. See document history at end for
details.
Link to old version.
Active Inductor Example
JFET Phono Preamp
This is an example only. It is not intended to be final or
complete design. It should only serve as an example of
equalization and active inductor calculations and not be built.
The SPICE verified two stage design
Low
Noise
2Stage
All
JFET Phono Preamp
would better serve
building an actual prototype.
Figure
1:
Schematic


Parts List


Q_{1}Q_{4} 
2N3918 nch jfet 
Q_{5},Q_{6} 
BS170 nch mosfet 
R_{1},R_{3},R_{5},R_{7}

220Ω, 5% 
R_{2},R_{4},R_{6},R_{8}

220Ω, 5% 
R_{2L}

221kΩ, 1% 
R_{2N}

32.4kΩ, 1%

C_{1N,a}

9.1nF, 1% or 5% 
C_{1N,b}

820pF, 1% or 5% 
C_{2N,a} 
3.3nF, 1% or 5% 

C_{2N,b}

91pF, 1% or 5% 
R_{1L} 
143kΩ, 1%

C_{L} 
6800µF, 25V
electrolytic

R_{9},R_{11}

1kΩ, 5%

R_{12}

82Ω, 5%

R_{13}

1kΩ, 5% (or
220Ω
see text)

C_{2}

100µF, 25V
electrolytic (or 47µF see text)

R_{15}

1kΩ pot (or 2kΩ see
text)

S_{1},S_{2} 
SPST reed relay,
normally closed, coil rated 10mA@5V




Beware the BS170 MOSFET is static sensitive. Follow ESD
procedures.
Remaining values are left for you to calculate. See text.

Initial Design Decisions
 Discrete voltage input design with 46db gain at 1kHz will amplify
5mV rms input to produce 1V rms
before attenuator.
 Q_{1}Q_{4} are 2N3918 nch jfet (6nV/rtHz noise
is
not
bad, you may choose a better device)
 I chose four devices because multiple parallel devices increase
S/N by sqrt(# of devices). In this case the effective
noise specification is bettered to 3nV/rtHz.
 Q_{5},Q_{6} are BS170 nch mosfet (commonly
available)
 v_{gs,max} of Q_{6}
of 20V limits V_{DD} due to
startup relays. Choose V_{DD} = 18V.
 Let bias of active inductor set bias to gate of Q6 to eliminate
coupling capacitor.
v_{g,Q6}
= 
(V_{DD}v_{gsQ5max})+v_{sgQ1max}
2

=

18V2V+8V
2

= 12V

 R_{2L} of active inductor functions as R_{1} of
passive
RIAA network.
 I chose to do the small signal classa design with a fourier
series
based distortion predictor tool out of convenience. Small signal
classa design is not in the scope of this article.
 Because of possibility of negative feedback from buffer stage
back to gain stage through power supply, I decided to recommend two
power supply taps.
Gain Stage Design
Although I used a convenient fourier series analysis tool to do the
small signal analysis, there were some design decisions. I wanted
to choose gate and source resistors small enough to make their noise
contribution insignificant compared to the JFET. This would lower
noise and allow the possiblity of noise improvement with better JFETs.
Resistor
noise
equation
(per
rtHz,
figure of merit, does not account for
bandwidth)

v_{nresistorrtHz} =
sqrt(4kTR)

Rearrange resistor noise equation to calculate equivalent input noise
resistance of JFET.
R =

v_{nresistorrtHz}^{2}
4kT

=

6nV^{2}
4 x 1.3806504e23 x 298.15ºK 
= 2.186371576kΩ 
I choose R
_{G} and R
_{S} 10 times lower to make their
noise contribution insignificant.
R1R8 = 220Ω.
Because the fourier series analysis resulting from this choice was
excellent, I made no further adjustments to these values.
Fourier Series Analysis of Q_{1}Q_{4} (excluding
drain load)
Analysis of Common Source Circuit
transistor type = JFET (Depletion mode FET approximation)
MOSFET constant = 1.1111111mS
threshold voltage = 3V
source resistor = 220Ω
Input signal (peak) = 7.0710678mV
Input bias = 0V
Output signal (peak) = 15.934985µA
Output bias = 4.4944528mA
Gain = 2.2535471mS
Total distortion = 3.5608755nA = 0.02234628% = 73.0159dB
Breakdown by harmonic
harmonic 
value 
percent 
dB 

0 
4.4944563mA 
28204.96173039% 
49.01dB 
DC Offset

1 
15.934985µA 
100.00000000% 
0.00dB 
Fundamental 
2 
3.5608755nA 
0.02234628% 
73.02dB 

Distortion figures for first stage are before RIAA equalization.
At the output of the RIAA network, they are lower because of the
downward sloping equalization. (A half or a little more for for
frequencies on or beginning the downward slope; in decibels, 6db lower)
RIAA Analysis
Refer
Calculating Passive RIAA
Equalization in article Phono Equalization
Calculations.
From this fourier analysis we can calculate R
_{1} of Passive
RIAA network (aka R
_{2L})
R_{2L} =

(Low frequency RIAA boost
relative to 1kHz) x (1kHz output voltage)
(Output signal current) x
(#parallel devices) 
=

10 x 1.414213562V
15.934985µA x 4 
= 221.8724339kΩ 
Round to nearest 1% value.
R_{2L} =
221kΩ
Given R
_{1}:R
_{2}
= 6.877358491
R_{2N} = 
221kΩ
6.877358491 
= 32.13443072kΩ 
Round to nearest 1% value.
R_{2N} =
32.4kΩ
Given R
_{1}C
_{1} = 2187µS
C_{1N} =

2187µS
221kΩ 
= 9.895927602nF

Round down to nearest 5% value: 9.1nF
Choose parallel 5% value to makeup remainder: 820pF
C_{1N} = 9.1nF + 820pF
Given R
_{1}C
_{2} = 750µS
C_{2N} =

750µS
221kΩ 
= 3.393665158nF

Round down to nearest 5% value: 3.3nF
Choose parallel 5% value to makeup remainder: 91pF
C_{2N} = 3.3nF + 91pF
Active Inductor Analysis
Refer article
Active Inductor Load.
 Choose R_{2L} for gain of overall circuit.
R
_{2L} chosen already in RIAA analysis.
BS170 specification: g
_{fs}
= 320mS @ 200mA.
Calculate MOSFET constant from g
_{fs}@i
_{D}
specification.
_{
}
k_{n}
= 
g_{fs}^{2}
4i_{D} 
=

320mS^{2}
4(200mA) 
= 128mA/V^{2
} 
_{
}Calculate new g
_{fs} from operating current and k
_{n}.
i
_{D} = 4.4944528mA x 4  (4V/221kΩ) =
17.9778112mA  18.09954751µA = 17.95971165mA
g
_{fs} = 2 x sqrt(k
_{n}i
_{D})
= 2 x sqrt(128mA/V
^{2} x 17.95971165mA) = 95.89250422mS
R_{1L} =

R_{2L}

Vbias
v_{T}+sqrt(i_{D}/k_{n}) 
1



=

221kΩ

6V
2V+sqrt(17.95971165mA/128mA/V^{2}) 
1



= 144.7507364kΩ 
Round to nearest 1% value:
R_{1L} =
143kΩ
 Choose C_{L} to set the pole frequency the desired amount
below the
passband. (equation (21))
C_{L} =

g_{fs}R_{1L}+1
2πf_{POLE}R_{1L} 
=

(95.94081162mS x 143kΩ)+1
2π x 5Hz x 143kΩ 
= 3.054113477mF

3300µF would work here. I would rather choose a larger common
value (
C_{L} =
6800µF) and solve for a lower pole.
f_{POLE} =

g_{fs}R_{1L}+1
2πC_{L}R_{1L} 
=

(95.94081162mS x 143kΩ)+1
2π x 6.8mF x 143kΩ 
= 2.245671674Hz 
 Determine if a bypass switch is needed to charge the capacitor on
startup.
Power on relay added at beginning of design.
Calculate charge time for C
_{L}:
Rearrange capacitor equation above and calculate time. (2V
presumes v
_{gs} not much more than v
_{T})
Δt =

CΔv
i_{D} 
=

6.8mF x 2V
4.4944528mA x 4 
= 756.4880868mSec

Q_{6} Circuit Design
My design goal here was reasonably low output impedance. 1kΩ
output impedance would have been low enough to minimize voltage loss
into a typical 47kΩ load. I choose 500Ω instead on the far chance
of driving a 600Ω load with a tolerable voltage loss.
Fourier Series Analysis of Q_{6} Circuit
Note: Bias and source resistor represent equivalent circuit
simplified
for analysis.
Original Design R
_{13} = 1kΩ, R
_{15} = 1kΩ. Large
2nd harmonic dominates distortion. Expect to be very tubey
Analysis of Common Source Circuit
transistor type = MOSFET
MOSFET constant = 128mS
threshold voltage = 2V
source resistor = 500Ω
Input signal (peak) = 1.4142136V
Input bias = 7V
Output signal (peak) = 2.7487914mA
Output bias = 9.4563897mA
Gain = 1.943689mS
Total distortion = 3.0913658µA = 0.11246273% = 58.9798dB
Breakdown by harmonic
harmonic 
value 
percent 
dB 

0 
9.4592357mA 
344.12344914% 
10.73dB 
DC Offset

1 
2.7487914mA 
100.00000000% 
0.00dB 
Fundamental 
2 
2.8643766µA 
0.10420495% 
59.64dB 

3 
206.32369nA 
0.00750598% 
82.49dB 

4 
18.586854nA 
0.00067618% 
103.40dB 

5 
1.875836nA 
0.00006824% 
123.32dB 

6 
202.86746pA 
0.00000738% 
142.64dB 

For a somewhat more neutral sound, consider that raising the bias
relative to the signal will lower the distortion.
Lower R
_{13} and raise R
_{15} to do this.
Alternative design: R
_{13} = 220Ω, R
_{15} = 2kΩ.
Analysis of Common Source Circuit
transistor type = MOSFET
MOSFET constant = 128mS
threshold voltage = 2V
source resistor = 200Ω
Input signal (peak) = 1.4142136V
Input bias = 11V
Output signal (peak) = 6.8377279mA
Output bias = 42.131413mA
Gain = 4.8350036mS
Total distortion = 4.7943711æA = 0.07011644% = 63.0836dB
Breakdown by harmonic
harmonic 
value 
percent 
dB 

0 
42.136007mA 
616.22819497% 
15.79dB 
DC Offset

1 
6.8377279mA 
100.00000000% 
0.00dB 
Fundamental 
2 
4.6032189µA 
0.06732088% 
63.44dB 

3 
181.69099nA 
0.00265718% 
91.51dB 

4 
8.965676nA 
0.00013112% 
117.65dB 

5 
495.5468pA 
0.00000725% 
142.80dB 

Miscellaneous Calculations
R
_{12} limits charge current through Q
_{6} to C
_{2}
to <500mA
R
_{12} >= 20V/500mA = 40Ω
Choose
R_{12} =
82Ω.
Want to set C
_{2} for as low a highpass pole as C
_{L}.
First
find
R
_{equiv} of pole. Output impedance of Q
_{6}
is the inverse of its operating ac transconductance g
_{fs}.
g
_{fs} = 2 x sqrt(k
_{n}i
_{D}) therefore
R_{outQ6} =

1
2 x sqrt(k_{n}i_{D}) 
=

1
2 x sqrt(128mA/V^{2}
x
42.131413mA) 
= 6.808665637Ω 
More tubey version:
R_{equiv} = (R_{outQ6
} R_{13}) + R_{15} = 
R_{outQ6 }x R_{13}
R_{outQ6 }+ R_{13} 
+ R_{15} = 1.006762621kΩ 
C_{2} =

1
2πf_{pole}R_{equiv} 
=

1
2π x 2.245671674Hz x
1.006762621kΩ 
= 70.39580633µF

Choose
C_{2} =
100µF.
The same calculations for the more neutral version give
R
_{equiv} = 2.006604273kΩ and C
_{2} = 35.31930408µF
Choose
C_{2} =
47µF.
Choose R
_{10} and R
_{14} to set 10mA through
relay coil.
R_{10} =

V_{DD}v_{COIL}
i_{COIL}

=

18V5V
10mA 
= 1.3kΩ 
Calculate load current from power supplies V
_{DD1 }and V
_{DD2}.
i
_{DD1} = i
_{Q1BIAS} x 4 + i
_{RELAYCOIL} =
4.4944528mA x 4 + 10mA = 27.9778112mA
i
_{DD2} = i
_{Q6BIAS} + i
_{RELAYCOIL = }9.4563897mA
+
10mA
=
19.4563897mA
(more tubey version)
i
_{DD2} = i
_{Q6BIAS} + i
_{RELAYCOIL = }42.131413mA
+
10mA
=
52.131413mA
(more neutral version)
Design Decisions Left to You
 Ri and Ci should be calculated per article Phono
Termination
Calculations
and
Calculator.
 Gate resistors were somewhat arbitrarily chosen. They seem
to be good values. I know that the 1kΩ values work with the
BS170. I have seen many jfet schematics without gate resistors at
all. Increase them if any oscillations occur.
 Relay components C_{1}
and C_{3} must be calculated as follows:
C
_{1} must be chosen by calculation or experimentation to
exceed C
_{L}
charge time calculated above (432.2244809mSec). C
_{3}
would then be
chosen for a somewhat longer delay to prevent a pop from the activation
of the other relay.
 This circuit and its analysis is only given as an example; change
everything if you like.
 A low noise 18V power supply. I recommend the circuit of
article Line Level Class A Power Supply.
^{1}There is a seeming discrepancy
in the fourier
analysis between the cited output bias and the same value given in the
analysis. The first value is the bias without any signal and the
second with a signal. This effect is created by the same asymetrical
transfer curve that gives us a desireable second order distortion
characteristic. The positive half of the signal is amplified more
than the negative half. As a result the dc bias is modulated by
the average signal level. This small component amounts to AM
demodulation of the music signal. Abstractly, I had already
anticipated this effect. I would be curious what effect this has
on the overall sound. Is is detrimental, or does it add an extra
euphonic bass urge?
Document History
January 2, 2010 Created
January 2, 2010 Minor Updates.
January 5, 2010 Recommend split power supply to prevent
feedback.
Update schematic to show change. Recommend specific power supply.
January 5, 2010 Choose relays S1 and S2, calculate their series
resistors, and calculate specific load current for each power supply
tap.
January 9, 2010 Added footnote explaining how fourier series
analysis
shows modulation of dc bias by music signal.
January 17, 2010 Added design criteria for classa biasing
decisions. Recalculate Active Inductor Analysis due to
miscalculation of g_{fs}.
January 23, 2010 Correct schematic in vicinity of Q_{4},
R_{7}, and R_{2N}.
January 27, 2010 Minor improvement to writing style.
March 11, 2010 Corrected for improper g_{fs} presumptions.
September 2, 2010 Added recommendation not to
build circuit.