

Copyright © 2008, 2009, 2010, 2011, 2014, 2015
Updated November 28, 2015. See document history at
end for details.
SPICE verified where indicated.
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The s variable will
represent seconds or the Laplace sdomain variable according to context.
Typical RIAA Equalization Bode Plot 
The design cycle involves initially calculating capacitances
from resistors appropriate for the desired gain and noise, rechoosing
the nearest appropriate standard capacitor values in the correct ratio,
then recalculating the resistances from which the nearest standard
values are chosen. This is because resistors are available in
tighter tolerances than are capacitors.
I presume for now that you know how to set the gain for these circuits and that calculating the RC networks are the difficult calculation.
Op amps are used for ease of illustration only. There is no intent to disparage discrete circuit designs.
A_{V1kHz}
A_{V<50Hz} 
= 
0.10103  (19.911018dB) 
A_{V<50Hz}
A_{V1kHz} 
= 
9.89808  (19.911018dB) 
This calculation applies to an RIAA impedance network that converts unequalized signal current into equalized output voltage. This includes inverting and current input stages.
T_{P1} = R_{1}C_{1} = 3180µs
T_{P2} = R_{2}C_{2} = 75µs
T_{Z} = (R_{1}R_{2})(C_{1}+C_{2})
=
318µs
T_{Z} is met when:
R_{1}/R_{2} ratio = 11.78
and when C_{1}/C_{2} ratio = 3.6
Inverting seriesparallel version verified by SPICE: Model.
(1) 
Z = R_{1}(1/sC_{1}) + R_{2}(1/sC_{2}) =  1
1/R_{1} + sC_{1} 
+ 
1
1/R_{2} + sC_{2} 
= 
R_{1}
sR_{1}C_{1}+1 
+ 
R_{2}
sR_{2}C_{2}+1 
(2) 
Z =  sR_{1}R_{2}C_{2}
+ R_{1}
+ sR_{1}R_{2}C_{1}
+ R_{2}
(sR_{1}C_{1} + 1)(sR_{2}C_{2} + 1) 
Time constant of reduced term is seen in (sT + 1).
Poles are clear, solve for zero.
(3) 
sR_{1}R_{2}C_{2} + R_{1} + sR_{1}R_{2}C_{1} + R_{2} = s(R_{1}R_{2}C_{2} + R_{1}R_{2}C_{1}) + (R_{1} + R_{2}) 
(4) 
T_{Z} =  R_{1}R_{2}C_{2}
+ R_{1}R_{2}C_{1}
R_{1} + R_{2} 
= 
R_{1}(75µs) + R_{2}(3180µs)
R_{1} + R_{2} 
= 318µs 
(5) 
R_{1}(75µs) + R_{2}(3180µs) = (R_{1}+R_{2})318µs 
(6) 
R_{1}(75µs318µs) + R_{2}(3180µs318µs) = 0 
(7) 
R_{1}
R_{2} 
= 
3180µs – 318µs
318µs  75µs 
= 11.777... = 11.7 
(8) 
C_{1}
C_{2} 
= 
T_{P1}/R_{1}
T_{P2}/R_{2} 
= 
3180µs/11.7R_{2}
75µs/R_{2} 
= 3.6 
T_{P1} = R_{1}C_{1} = 3180µs
T_{P2} = R_{2}C_{2} = 75µs
T_{Z1} = 318µs
T_{Z2} = 3.18µs
R_{1}, R_{2}, and R_{3} in ratio 217.173913 :
17.67514356
: 1 will yield correct
time constants for zeros if C_{1} and C_{2} are chosen
to yield correct poles.
R_{3b} = 
(235.8490566)R_{3} A_{V<50Hz} 
= (0.2382778)R_{3}
for RIAA
standard 40dB gain at 1kHz 
SPICE model of noninverting seriesparallel riaa circuit with extra
zero verifying correct adjustments for gain.
SPICE Model
See Lownoise
Hybrid
Opamp/Discrete
Phono
Preamp for a complete
design example of this type.
(1) 
Z = R_{1}(1/sC_{1}) + R_{2}(1/sC_{2}) + R_{3} =  R_{1}
sR_{1}C_{1} + 1 
+ 
R_{2}
sR_{2}C_{2} + 1 
+ R_{3} 
(2) 
Z =  sR_{1}R_{2}C_{2}
+
R_{1} +
sR_{2}R_{1}C_{1} + R_{2} + (sR_{1}C_{1}
+
1)(sR_{2}C_{2} + 1)R_{3}
(sR_{1}C_{1} + 1)(sR_{2}C_{2} + 1) 
(3) 
Z =  sR_{1}R_{2}C_{2}
+
R_{1} +
sR_{2}R_{1}C_{1} + R_{2} + (s^{2}R_{1}C_{1}R_{2}C_{2}
+
sR_{1}C_{1} + sR_{2}C_{2} + 1)R_{3}
(sR_{1}C_{1} + 1)(sR_{2}C_{2} + 1) 
(4) 
Z =  sR_{1}R_{2}C_{2}
+
R_{1} +
sR_{2}R_{1}C_{1} + R_{2} + s^{2}R_{1}C_{1}R_{2}C_{2}R_{3}
+ s(R_{1}C_{1}R_{3} + R_{2}C_{2}R_{3})
+
R_{3}
(sR_{1}C_{1} + 1)(sR_{2}C_{2} + 1) 
(5) 
Z =  s^{2}R_{1}C_{1}R_{2}C_{2}R_{3}
+ s(R_{1}R_{2}C_{2} + R_{2}R_{1}C_{1}
+ R_{1}C_{1}R_{3}
+ R_{2}C_{2}R_{3})
+ (R_{1} + R_{2} + R_{3})
(sR_{1}C_{1} + 1)(sR_{2}C_{2} + 1) 
Time constant of reduced term is seen in (sT + 1).
Poles are clear, solve for zeros.
(6) 
s^{2}R_{1}C_{1}R_{2}C_{2}R_{3} + s(R_{1}R_{2}C_{2} + R_{2}R_{1}C_{1} + R_{1}C_{1}R_{3} + R_{2}C_{2}R_{3}) + (R_{1} + R_{2} + R_{3}) = 0 
(7) 
s^{2}(3180µs)(75µs)R_{3} + s(R_{1}(75µs) + R_{2}(3180µs) + (3180µs)R_{3} + (75µs)R_{3}) + (R_{1} + R_{2} + R_{3}) = 0 
(8) 
s^{2}(238.5n(S^{2}))R_{3} + s((R_{1} + R_{3})(75µs) + (R_{2} + R_{3})(3180µs)) + (R_{1} + R_{2} + R_{3}) = 0 
(9) 
s^{2}  R_{3}(238.5n(S^{2}))
R_{1} + R_{2} + R_{3} 
+ s  (R_{1}
+ R_{3})75µs
+
(R_{2} + R_{3})3180µs
R_{1} + R_{2} + R_{3} 
+ 1 = 0 
(10) 
= s^{2}T_{Z1}T_{Z2} + s(T_{Z1} + T_{Z2}) + 1 = 0 
(11) 
T_{Z1}T_{Z2} =  R_{3}(238.5n(s^{2}))
R_{1} + R_{2} + R_{3} 
= 1.01124n(s^{2}) 
(12) 
R_{3}
R_{1} + R_{2} + R_{3} 
= 4.24m 
(13) 
R_{3} = 4.24m(R_{1} + R_{2} + R_{3}) 
(14) 
R_{1} + R_{2} + R_{3} = 235.8490566 R_{3} 
(15) 
R_{1} + R_{2} = 234.8490566 R_{3} 
(16) 
T_{Z1} + T_{Z2} =  (R_{1} + R_{3})75µs
+
(R_{2}
+ R_{3})3180µs
R_{1} + R_{2} + R_{3} 
= 321.18µs 
(17) 
(R_{1} + R_{3})75µs + (R_{2} + R_{3})3180µs = (R_{1} + R_{2} + R_{3})321.18µs 
(18) 
R_{1}(75µs  321.18µs) + R_{2}(3180µs  321.18µs) + R_{3}(75µs + 3180µs  321.18µs) = 0 
(19) R_{1}(246.18µs) + R_{2}(2858.82µs) + R_{3}(2933.82µs) = 0
(19) 
R_{1}(246.18µs) + R_{2}(2858.82µs) + R_{3}(2933.82µs) = 0 
The two equations (15) and (19) in three variables suggest R_{1}, R_{2}, R_{3} variable but in fixed ratio as intuition would suggest.
Choose R_{3} = 1 to solve for this ratio.
Then equation (15) becomes:
(20) R_{1} + R_{2} = 234.8490566
Then equation (19)
simplifies to:
(21) R_{1}(246.18µs) + R_{2}(2858.82µs) =
2933.82µs
Using simultaneous linear equations (18) and (19), solve for R_{1} and R_{2}:
(22) 
Det =  1 246.18µ 
1 2858.82µ 
= 2858.82µ  246.18µ = 3105µ 
(23) 
R_{1} = 
3105µ 
= 
(234.8490566)(
2858.82µ)  2933.82µ
3105µ 
(24) 
R_{1} = 217.173913Ω 
(25) 
R_{2} = 
3105µ 
= 
2933.82µ 
(234.8490566)(246.18µ)
3105µ 
(26) 
R_{2} = 17.67514356Ω 
R_{1}, R_{2}, and R_{3} in ratio 217.173913
:
17.67514356 : 1 will yield
correct time constants for zeros if C_{1} and C_{2} are
chosen to yield
correct poles.
(27) 
A_{V<50Hz} = 
R_{1} + R_{2} + R_{3a}
+
R_{3b} R_{3b} 
= 
(217.173913 + 17.67514356 + 1)R_{3} R_{3b} 
= 
(235.8490566)R_{3} R_{3b} 
(28) 
R_{3b} = 
(235.8490566)R_{3} A_{V<50Hz} 
This calculation applies to an RIAA network normally used for passive equalization. Parallel topologies are also preferred for discrete transistor designs because stray circuit capacitances can be compensated in C_{2} and drain/collector resistances in R_{1}. Application of Thevenin’s theorem moves R_{1} into parallel with C_{1} and R_{2}, opening up the use of the same network for inverting and current input applications.
T_{P1} = 3180µs
T_{P2} = 75µs
T_{Z} = 318µs = R_{2}C_{1}
R_{1}C_{2} = 750µs
R_{1}C_{1} = 2187µs
R_{1}:R_{2} = 6.877358491
C_{1}:C_{2} = 2.916
Passive parallel version verified by SPICE: Model, Inverse RIAA Subckt used in model.
(1) 
Z = R_{1}(R_{2}+(1/sC_{1})))(1/sC_{2}) =  R_{1}   sR_{2}C_{1}
+
1
sC_{1} 
  1
sC_{2} 
(2) 
Z =  1

  1
sC_{2} 
= 
1

  1
sC_{2} 
(3) 
Z =  sR_{1}R_{2}C_{1}
+
R_{1}
s(R_{1}C_{1} + R_{2}C_{1}) + 1 
  1
sC_{2} 
= 
1

(4) 
Z =  1

(5) 
Z =  sR_{1}R_{2}C_{1}
+
R_{1}
s^{2}R_{1}R_{2}C_{1}C_{2} + s(R_{1}C_{1} + R_{2}C_{1} + R_{1}C_{2}) + 1 
Zero is clear:
(6) 
sT_{Z} + 1 =  sR_{1}R_{2}C_{1}
+
R_{1}
R_{1} 
, therefore T_{Z} = R_{2}C_{1} = 318µs 
Solve for poles:
(7) 
s^{2}T_{P1}T_{P2} + s(T_{P1} + T_{P2}) + 1 = 0 
(8) T_{P1}T_{P2 }= R_{1}R_{2}C_{1}C_{2} = (R_{2}C_{1})R_{1}C_{2} = T_{Z}R_{1}C_{2} (from equations (5) and (7))
(8) 
T_{P1}T_{P2 }= R_{1}R_{2}C_{1}C_{2} = (R_{2}C_{1})R_{1}C_{2} = T_{Z}R_{1}C_{2} (from equations (5) and (7)) 
(9) 
R_{1}C_{2} =  T_{P1}T_{P2}
T_{Z} 
= 
(3180µs)(75µs)
318µs 
= 750µs 
(10) 
T_{P1} + T_{P2} = R_{1}C_{1} + R_{2}C_{1} + R_{1}C_{2} (from equations (5) and (7)) 
(11) 
3180µs + 75µs = R_{1}C_{1} + 318µs + 750µs 
(12) 
R_{1}C_{1} = 3180µs + 75µs  318µs  750µs = 2187µs 
(13) 
R_{1}
R_{2} 
= 
R_{1}C_{1}
R_{2}C_{1} 
= 
2187µs
318µs 
= 6.877358491 
(14) 
C_{1}
C_{2} 
= 
R_{1}C_{1}
R_{1}C_{2} 
= 
2187µs
750µs 
= 2.916 
This calculation adds an extra 50kHz zero to an RIAA network
normally used for passive equalization. Parallel topologies are
also preferred for discrete transistor designs because stray circuit
capacitances can be compensated in C_{2} and drain/collector
resistances
in R_{1}. The addition of R_{3} in series with C_{2}
to add the
extra zero
somewhat diminishes this advantage, complicating the compensation for
stray capacitance. Application of Thevenin’s theorem moves R_{1}
into parallel with C_{1} and R_{2}, opening up the use
of the same
network
for inverting and current input applications.
(1) 
Z = R_{1}  (R_{2}+1/sC_{1})

(R_{3} +
1/sC_{2}) = R_{1}  
sR_{2}C_{1}+1
sC_{1} 
 
sR_{3}C_{2}+1
sC_{2} 
(2)  1 
1 

Z = 

= 




(3) 
R_{1}(sR_{2}C_{1}+1)(sR_{3}C_{2}+1)  R_{1}(sR_{2}C_{1}+1)(sR_{3}C_{2}+1)  
Z = 

= 


(s^{2}R_{2}R_{3}C_{1}C_{2}
+
s(R_{2}C_{1}+R_{3}C_{2}) +1) + (s^{2}R_{1}R_{3}C_{1}C_{2} + sR_{1}C_{1}) + (s^{2}R_{1}R_{2}C_{1}C_{2} + sR_{1}C_{2}) 
s^{2}(R_{2}R_{3}C_{1}C_{2}+R_{1}R_{3}C_{1}C_{2}+R_{1}R_{2}C_{1}C_{2})
+ s(R_{2}C_{1}+R_{3}C_{2}+R_{1}C_{1}+R_{1}C_{2}) + 1 
(4) 
s^{2}T_{P1}T_{P2}
+ s(T_{P1}+T_{P2}) + 1 = 0 
(5) 
T_{P1}T_{P2} = R_{2}R_{3}C_{1}C_{2} + R_{1}R_{3}C_{1}C_{2} + R_{1}R_{2}C_{1}C_{2} = T_{Z1}T_{Z2} + T_{Z2}R_{1}C_{1} + T_{Z1}R_{1}C_{2} 
(6) 
T_{P1}+T_{P2} = R_{2}C_{1} + R_{3}C_{2} + R_{1}C_{1} + R_{1}C_{2} = T_{Z1} + T_{Z2} + R_{1}C_{1} + R_{1}C_{2} 
(7) 
3.18µT_{A} + 318µT_{B} = 237.489n 
(8) 
T_{A} + T_{B} = 2.93382m 
(9) 
Det =  3.18µ 1 
318µ 1 
= 3.18µ – 318µ = –314.82µ 
(10) 
T_{A} = 
–314.82µ 
= 
237.489n –
(318µ)(2.93382m)
–314.82µ 
(11) 
T_{A} = 2209.09µs = R_{1}C_{1} 
(12) 
T_{B} = 
–314.82µ 
= 
(3.18µ)(2.93382m) – 237.489n
–314.82µ 
(13) 
T_{B} = 724.73µs = R_{1}C_{2} 
(14) 
R_{1}
R_{3} 
= 
T_{B}
T_{Z2} 
= 
724.73µs
3.18µs 
= 
227.902 
(15) 
R_{1}
R_{2} 
= 
T_{A}
T_{Z1} 
= 
2209.09µs
318µs 
= 
6.94682 
(16) 
R_{2}
R_{3} 
= 
R_{1}/R_{3}
R_{1}/R_{2} 
= 
227.902
6.94682 
= 
32.8066 
Sometimes it is desireable to divide the equalization between two
stages. All practical circuits put the 3180µs pole and the 318µs
zero in one stage leaving the 75µs pole to the other.
Circuit
1:
Series/Parallel 
(2) 

R_{1} 
sR_{1}R_{2}C_{1}
+
R_{1} + R_{2} 

Z = R_{2} + 

= R_{2} + 

= 



sR_{1}C_{1}
+ 1 
sR_{1}C_{1}
+ 1 
(4) 
T_{Z1} = 
R_{1}R_{2}C_{1}
R_{1} + R_{2} 
= (R_{1}  R_{2})C_{1} = 318µs 
(8) 
(T_{P1}/T_{Z1})  

= R_{1} 


(9) 
1
R_{1} 
+ 
1
R_{2} 
= 
(T_{P1}/T_{Z1})
R_{1} 
, therefore 
1
R_{2} 
= 
(T_{P1}/T_{Z1}) –
1
R_{1} 
(10) 
R_{1} = 
T_{P1}
T_{Z1} 
– 1  R_{2} 
Circuit
2:
Parallel/Series 
(2) 

sR_{2}R_{1}C_{1}
+
R_{2} 

Z = 

= 



s(R_{2}
+ R_{1})C_{1}
+ 1 
(4) 
T_{Z1}
= 
R_{2}R_{1}C_{1}
R_{2} 
= R_{1}C_{1} = 318µs 
(8) 
R_{2} = 
T_{P1}
T_{Z1} 
– 1  R_{1} 
75µs
Lowpass
Stage
Common
to
Both 
If you have comments on the calculations email me at contact@waynestegall.com
The RIAA equalization calculations above presume that no
equalization is needed for the input loop itself. For voltage
input designs, correct RC loading at the preamp input meet these
conditions, although not perfectly. Reading reviews of current
input designs did not mention any special compensation that I
remember. However when I reexamined this issue I found the
following result: The virtual short at the input reduces the
equivalent input loop to a RL response with a low cutoff frequency,
which would greatly attenuate the treble. This is because the
complex pole pair of the full second order circuit diverges into two
real poles below a Q of 0.5 (The second pole is pushed far into the
ultrasonic region with the Q values involved). Therefore it is
necessary to add a zero of the same value to the compensation circuit,
perhaps in a second stage. I present this result only after I
verified it by examining a patent for this type of circuit issued in
1984 (That it expired 17 years later in 2001 makes this a public domain
design.) Because in the winding of an inductor both R and L
increase with the number of turns, cartridges whose windings are made
with the same gauge magnet wire may all have the same or similar RL
response. This suggests the selection of a fixed compensation
zero as a design compromise. Others may want to have an
adjustable zero to tailor the compensation to their desired cartridge.
T_{Z3} =  L
R 
f_{Z3} =  R
2πL 
Recommended
circuit
allows
placement
of
compensation
in
either
stage. 
R_{1} = 
3180µs
T_{Z3} 
– 1  R_{2} 
R_{4} = 
T_{Z3}
75µs 
– 1  R_{3} 
Z_{GAIN} = 
(R_{1} + R_{2})R_{5}
R_{4} 
SeriesParallel
in
both
stages
allowed
by
adjustment
in
first
stage 
Discrete Full SeriesParallel Circuit 
Note: Incomplete
schematic only illustrates equalization topology, biasing is likely
incorrect 
R_{1} = 
3180µs
T_{Z3} 
– 1  R_{2} 
ParallelSeries in both stages allowed by adjustment in second stage 
R_{4} = 
T_{Z3}
75µs 
– 1  R_{3} 
Currentinput
equalization
at
a
plausibly
typical
cartridge
LR
frequency
of
212.2Hz
shows
much flatter equalization than voltage input designs. 
