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Updated March 17, 2014. See document
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SPICE verified where indicated.
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The s variable
will represent seconds or the Laplace sdomain variable
according to context.
The intention of this document is to give the audio hobbyist mathematical basis to calculate the resistor and capacitor values in the RIAA equalization network of a phono preamp. I searched the internet for this same information and could not find it. As a result my curiosity compelled me to make the calculations myself. The bode plot shown is of typical equalization curve with poles at 3180µs and 75µs, and a zero at 318µs. A Gain of 60dB at DC and 40dB at 1kHz is typical of a MM voltage amplification stage. Many hold that an additional zero at 3.18µs will compensate for a corresponding pole used in phono cutting amplifiers to put a practical limit on the preequalization gain at 50kHz.
The design cycle involves initially calculating capacitances from resistors appropriate for the desired gain and noise, rechoosing the nearest appropriate standard capacitor values in the correct ratio, then recalculating the resistances from which the nearest standard values are chosen. This is because resistors are available in tighter tolerances than are capacitors.
I presume for now that you know how to set the gain for these circuits and that calculating the RC networks are the difficult calculation.
Op amps are used for ease of illustration only. There is no intent to disparage discrete circuit designs. 

A_{V1kHz}
A_{V<50Hz} 
= 
0.10103  (19.911018dB) 
A_{V<50Hz}
A_{V1kHz} 
= 
9.89808  (19.911018dB) 
This calculation applies to an RIAA impedance network that converts unequalized signal current into equalized output voltage. This includes inverting and current input stages.
T_{P1} = R1C1 = 3180µs
T_{P2} = R2C2 = 75µs
T_{Z} = (R1R2)(C1+C2) = 318µs
T_{Z} is met when:
R1/R2 ratio = 11.78
and when C1/C2 ratio = 3.6
Inverting seriesparallel version verified by SPICE: Model.
(1) 


1 

1 

R1 

R2 

Z = 
R1(1/sC1) + R2(1/sC2) = 
+ 
= 
+ 




1/R1 + sC1 

1/R2 + sC2 

sR1C1+1 

sR2C2+1 
(2) 

sR1R2C2 + R1 + sR1R2C1 + R2 

Z = 



(sR1C1 + 1)(sR2C2 + 1) 
Time constant of reduced term is seen in (sT + 1).
Poles are clear, solve for zero.
(3) sR1R2C2 + R1 + sR1R2C1 + R2 = s(R1R2C2 + R1R2C1) + (R1 + R2)
(4) 

R1R2C2 + R1R2C1 

R1(75µs) + R2(3180µs) 



T_{Z} = 
= 
= 
318µs 



R1 + R2 

R1 + R2 


(5) R1(75µs) + R2(3180µs) = (R1+R2)318µs
(6) R1(75µs318µs) + R2(3180µs318µs) = 0
(7) 
R1 

3180µs – 318µs 



= 
= 
11.777... = 11.7 


R2 

318µs  75µs 


(8) 
C1 

T_{P1}/R1 

3180µs/11.7R2 



= 
= 
= 
3.6 


C2 

T_{P2}/R2 

75µs/R2 


T_{P1} = R1C1 = 3180µs
T_{P2} = R2C2 = 75µs
T_{Z1} = 318µs
T_{Z2} = 3.18µs
R1, R2, and R3 in ratio 217.173913 : 17.67514356 : 1 will yield
correct time constants for zeros if C1 and C2 are chosen to
yield correct poles.
R3b = 
(235.8490566)R3 A_{V<50Hz} 
= (0.2382778)R3 for
RIAA standard 40dB gain at 1kHz 
SPICE model of noninverting seriesparallel riaa circuit with
extra zero verifying correct adjustments for gain.
SPICE Model
See Lownoise
Hybrid Opamp/Discrete Phono Preamp for
a complete design example of this type.
(1) 

R1 

R2 



Z = R1(1/sC1) + R2(1/sC2) + R3 = 
+ 
+ 
R3 



sR1C1 + 1 

sR2C2 + 1 


(2) 

sR1R2C2 + R1 + sR2R1C1 + R2 + (sR1C1 + 1)(sR2C2 + 1)R3 

Z = 



(sR1C1 + 1)(sR2C2 + 1) 
(3) 

sR1R2C2 + R1 + sR2R1C1 + R2 + (s^{2}R1C1R2C2 + sR1C1 + sR2C2 + 1)R3 

Z = 



(sR1C1 + 1)(sR2C2 + 1) 
(4) 

sR1R2C2 + R1 + sR2R1C1 + R2 + s^{2}R1C1R2C2R3 + s(R1C1R3 + R2C2R3) + R3 

Z = 



(sR1C1 + 1)(sR2C2 + 1) 
(5) 

s^{2}R1C1R2C2R3 + s(R1R2C2 + R2R1C1 + R1C1R3 + R2C2R3) + (R1 + R2 + R3) 

Z = 



(sR1C1 + 1)(sR2C2 + 1) 
Time constant of reduced term is seen in (sT + 1).
Poles are clear, solve for zeros.
(6) s^{2}R1C1R2C2R3 + s(R1R2C2 + R2R1C1 + R1C1R3 + R2C2R3) + (R1 + R2 + R3) = 0
(7) s^{2}(3180µs)(75µs)R3 + s(R1(75µs) + R2(3180µs) + (3180µs)R3 + (75µs)R3) + (R1 + R2 + R3) = 0
(8) s^{2}(238.5n(S^{2}))R3 + s((R1 + R3)(75µs) + (R2 + R3)(3180µs)) + (R1 + R2 + R3) = 0





(10) = s^{2}T_{Z1}T_{Z2} + s(T_{Z1} + T_{Z2}) + 1 = 0
(11) 

R3(238.5n(s^{2})) 


T_{Z1}T_{Z2} = 
= 1.01124n(s^{2}) 



R1 + R2 + R3 

(12) 
R3 


= 4.24m 


R1 + R2 + R3 

(13) R3 = 4.24m(R1 + R2 + R3)
(14) R1 + R2 + R3 = 235.8490566 R3
(15) R1 + R2 = 234.8490566 R3
(16) 

(R1 + R3)75µs + (R2 + R3)3180µs 


T_{Z1} + T_{Z2} = 
= 321.18µs 



R1 + R2 + R3 

(17) (R1 + R3)75µs + (R2 + R3)3180µs = (R1 + R2 + R3)321.18µs
(18) R1(75µs  321.18µs) + R2(3180µs  321.18µs) + R3(75µs + 3180µs  321.18µs) = 0
(19) R1(246.18µs) + R2(2858.82µs) + R3(2933.82µs) = 0
The two equations (15) and (19) in three variables suggest R1, R2, R3 variable but in fixed ratio as intuition would suggest.
Choose R3 = 1 to solve for this ratio.
Then equation (15)
becomes:
(20) R1 + R2 = 234.8490566
Then equation (19)
simplifies to:
(21) R1(246.18µs) + R2(2858.82µs) = 2933.82µs
Using simultaneous linear equations (18) and (19), solve for R1 and R2:



(23) 



(234.8490566)( 2858.82µ)  2933.82µ 


R1 = 
= 



3105µ 

3105µ 
(24) R1 = 217.173913Ω
(25) 



2933.82µ  (234.8490566)(246.18µ) 


R2 = 
= 



3105µ 

3105µ 
(26) R2 = 17.67514356Ω
R1, R2, and R3 in ratio 217.173913 : 17.67514356 : 1 will yield
correct time constants for zeros if C1 and C2 are chosen to
yield correct poles.
(27) 
A_{V<50Hz} = 
R1 + R2 + R3a + R3b R3b 
= 
(217.173913 + 17.67514356 +
1)R3 R3b 
= 
(235.8490566)R3 R3b 
(28) 
R3b = 
(235.8490566)R3 A_{V<50Hz} 
This calculation applies to an RIAA network normally used for passive equalization. Parallel topologies are also preferred for discrete transistor designs because stray circuit capacitances can be compensated in C2 and drain/collector resistances in R1. Application of Thevenin’s theorem moves R1 into parallel with C1 and R2, opening up the use of the same network for inverting and current input applications.
T_{P1} = 3180µs
T_{P2} = 75µs
T_{Z} = 318µs = R2C1
R1C2 = 750µs
R1C1 = 2187µs
R1:R2 = 6.877358491
C1:C2 = 2.916
Passive parallel version verified by SPICE: Model, Inverse RIAA Subckt used in
model.









(3) 

sR1R2C1 + R1 

1 

1 


Z = 
 
= 



s(R1C1 + R2C1) + 1 

sC2 


(4) 

1 

Z = 



s(R1C1 + R2C1) + 1 + s^{2}R1R2C1C2 + sR1C2 





sR1R2C1 + R1 
(5) 

sR1R2C1 + R1 

Z = 



s^{2}R1R2C1C2 + s(R1C1 + R2C1 + R1C2) + 1 
Zero is clear:
(6) 

sR1R2C1 + R1 


sT_{Z} + 1 = 
, therefore T_{Z} = R2C1 = 318µs 



R1 

Solve for poles:
(7) s^{2}T_{P1}T_{P2} + s(T_{P1} + T_{P2}) + 1 = 0
(8) T_{P1}T_{P2 }= R1R2C1C2 = (R2C1)R1C2 = T_{Z}R1C2 (from equations (5) and (7))
(9) 

T_{P1}T_{P2} 

(3180µs)(75µs) 


R1C2 = 
= 
= 750µs 



T_{Z} 

318µs 

(10) T_{P1} + T_{P2} = R1C1 + R2C1 + R1C2 (from equations (5) and (7))
(11) 3180µs + 75µs = R1C1 + 318µs + 750µs
(12) R1C1 = 3180µs + 75µs  318µs  750µs = 2187µs
(13) 
R1 

R1C1 

2187µs 


= 
= 
= 6.877358491 


R2 

R2C1 

318µs 

(14) 
C1 

R1C1 

2187µs 


= 
= 
= 2.916 


C2 

R1C2 

750µs 

This calculation adds an extra 50kHz zero to an RIAA network
normally used for passive equalization. Parallel
topologies are also preferred for discrete transistor designs
because stray circuit capacitances can be compensated in C2 and
drain/collector resistances in R1. The addition of R3 in
series with C2 to add the extra zero somewhat diminishes this
advantage, complicating the compensation for stray
capacitance. Application of Thevenin’s theorem moves R1
into parallel with C1 and R2, opening up the use of the same
network for inverting and current input applications.
(1) 
Z = R1  (R2+1/sC1)  (R3
+ 1/sC2) = R1  
sR2C1+1
sC1 
 
sR3C2+1
sC2 
(2)  1 
1 

Z = 

= 




(3) 
R1(sR2C1+1)(sR3C2+1)  R1(sR2C1+1)(sR3C2+1)  
Z = 

= 


(s^{2}R2R3C1C2 +
s(R2C1+R3C2) +1) + (s^{2}R1R3C1C2 + sR1C1) + (s^{2}R1R2C1C2 + sR1C2) 
s^{2}(R2R3C1C2+R1R3C1C2+R1R2C1C2)
+ s(R2C1+R3C2+R1C1+R1C2) + 1 
(4) 
s^{2}T_{P1}T_{P2}
+ s(T_{P1}+T_{P2}) + 1 = 0 
(5) 
T_{P1}T_{P2} = R2R3C1C2 + R1R3C1C2 + R1R2C1C2 = T_{Z1}T_{Z2} + T_{Z2}R1C1 + T_{Z1}R1C2 
(6) 
T_{P1}+T_{P2} = R2C1 + R3C2 + R1C1 + R1C2 = T_{Z1} + T_{Z2} + R1C1 + R1C2 
Using simultaneous linear equations (7) and (8), solve for T_{A} and T_{B}:



(10) 



237.489n  (318µ)(2.93382m) 


T_{A} = 
= 



314.82µ 

314.82µ 
(11) T_{A} = 2209.09µs = R1C1
(12) 



(3.18µ)(2.93382m)  237.489n 


T_{B} = 
= 



314.82µ 

314.82µ 
(13) T_{B} = 724.73µs = R1C2
(14) 
R1
R3 
= 
T_{B}
T_{Z2} 
= 
724.73µs
3.18µs 
= 
227.902 
(15) 
R1
R2 
= 
T_{A}
T_{Z1} 
= 
2209.09µs
318µs 
= 
6.94682 
(16) 
R2
R3 
= 
R1/R3
R1/R2 
= 
227.902
6.94682 
= 
32.8066 
Sometimes it is desireable to divide the equalization between
two stages. All practical circuits put the 3180µs pole and
the 318µs zero in one stage leaving the 75µs pole to the other.
Circuit 1: Series/Parallel 
(2) 

R1 
sR1R2C1
+ R1 + R2 

Z = R2 + 

= R2 + 

= 



sR1C1 +
1 
sR1C1 +
1 
(4) 
T_{Z1} = 
R1R2C1
R1 + R2 
= (R1  R2)C1 = 318µs 
(8) 
(T_{P1}/T_{Z1})  

= R1 


(9) 
1
R1 
+ 
1
R2 
= 
(T_{P1}/T_{Z1})
R1 
, therefore 
1
R2 
= 
(T_{P1}/T_{Z1})
– 1
R1 
(10) 
R1 = 

T_{P1}
T_{Z1} 
– 1  R2 
Circuit 2: Parallel/Series 
(2) 

sR2R1C1
+ R2 

Z = 

= 



s(R2 +
R1)C1 + 1 
(4) 
T_{Z1}
= 
R2R1C1
R2 
= R1C1 = 318µs 
(8) 
R2 = 

T_{P1}
T_{Z1} 
– 1  R1 
75µs Lowpass Stage Common to Both 
If you have comments on the calculations email me at contact@waynestegall.com
The RIAA equalization calculations above presume that no
equalization is needed for the input loop itself. For
voltage input designs, correct RC loading at the preamp input
meet these conditions, although not perfectly. Reading
reviews of current input designs did not mention any special
compensation that I remember. However when I reexamined
this issue I found the following result: The virtual short
at the input reduces the equivalent input loop to a RL response
with a low cutoff frequency, which would greatly attenuate the
treble. This is because the complex pole pair of the full
second order circuit diverges into two real poles below a Q of
0.5 (The second pole is pushed far into the ultrasonic region
with the Q values involved). Therefore it is necessary to add a
zero of the same value to the compensation circuit, perhaps in a
second stage. I present this result only after I verified
it by examining a patent for this type of circuit issued in 1984
(That it expired 17 years later in 2001 makes this a public
domain design.) Because in the winding of an inductor both
R and L increase with the number of turns, cartridges whose
windings are made with the same gauge magnet wire may all have
the same or similar RL response. This suggests the
selection of a fixed compensation zero as a design
compromise. Others may want to have an adjustable zero to
tailor the compensation to their desired cartridge.
T_{Z3} =  L
R 
f_{Z3} =  R
2πL 
Recommended circuit allows placement of
compensation in either stage. 
R_{1} = 

3180µs
T_{Z3} 
– 1  R_{2} 
R_{4} = 

T_{Z3}
75µs 
– 1  R_{3} 
Z_{GAIN} = 
(R_{1} + R_{2})R_{5}
R_{4} 
SeriesParallel in both stages allowed by
adjustment in first stage 
Discrete Full SeriesParallel Circuit 
Note:
Incomplete schematic only illustrates equalization
topology, biasing is likely incorrect 
R_{1} = 

3180µs
T_{Z3} 
– 1  R_{2} 
ParallelSeries in both stages allowed by adjustment in second stage 
R_{4} = 

T_{Z3}
75µs 
– 1  R_{3} 
Currentinput equalization at a plausibly
typical cartridge LR frequency of 212.2Hz shows much
flatter equalization than voltage input designs. 
