Copyright © 2010 by Wayne Stegall
Updated March 26, 2011. See document history at end for
details.
LowNoise TwoStage JFET Phono Preamp
This circuit is SPICE verified. It is only provided for design
assistance. Its final validity awaits someone to prototype it.
Figure
1:
Schematic


Parts List


* R_{1} 
47kΩ, 1/8V

* C_{1} 
100pF, metal film

Q_{1}Q_{5} 
LSK170A nch jfet 
Q_{6} 
LSK170C nch jfet 
R_{2},R_{3},R_{4},R_{5}

56Ω, 5%, 1/8W

R_{6} 
2kΩ, 1%, 1/2W

** C_{2a} 
39nF, 1% plastic
film 
** C_{2b} 
2.7nF, 1% plastic
film 
C_{3} 
3.9µF polyethylene 
R_{7} 
10MΩ, 1%, 1/8W


R_{8} 
442kΩ, 1%, 1/8W

R_{9} 
1.1kΩ, 5%, 1/2W

R_{10} 
2kΩ, 1%, 1/8W

** C_{4a} 
160nF, 1% plastic
film

** C_{4b} 
16nF, 1% plastic film 
R_{11} 
18.2kΩ, 1%, 1/8W

R_{12} 
2.4kΩ, 5%, 1/2W

R_{13} 
2.4kΩ, 5%, 1/2W

R_{14} 
100kΩ, 5%, 1/8W

C_{5} 
10uF polyethylene
or 180µF electrolytic, see text


* Default values. R_{1} and C_{1} should be
calculated to match cartridge LCR per article Phono
Termination
Calculations
and
Calculator.
** Capacitor pairs are connected in parallel.
Verify parts list to final SPICE model.

Initial Design Decisions
 Design approach is to use higher voltage power supply to allow
larger gain with conventional class A circuits.
 Want 5mV_{RMS} to produce 1V_{RMS} at
output at 1kHz. This amounts to 46dB of gain at 1kHz. Most
gain references and calculations are relative to 66dB of gain below
50Hz. Altered gain goal to standard RIAA 40dB of gain at 1kHz to
lower distortion.
 Initially choose 48V power supplies because of unsatisfactory
results with 40V supply in prior design cycle.
 Q_{1}Q_{5} are LSK170A nch jfet (chosen for
excellent 1nV/√Hz noise specification). Use A grade for more
possible gain.
 Desireable self bias (V_{gdc} = 0V, all bias set by
source resistor) on first stage is allowed by small input signal.
(Signal will clip if peak is greater than V_{p0} of
0.4025156V; distortion considerations require even more headroom.)
 That a larger signal drives second stage requires more bias than
self bias would allow. Use gate biasing for second stage.
 I chose four devices for stage one because multiple parallel
devices devices
increase
S/N by sqrt(# of devices). In this case halving the effective
noise in the source circuit and to some extent overall.
 Q_{6} is LSK170C nch jfet. Biasing concerns
disadvantage MOSFET here.
 Because of possibility of negative feedback from buffer stage
back to gain stage through power supply, I decided to recommend three
power supply taps.
Figure
2:
Stage
with
75µS
pole
(red
curve)
will
boost
signal out of
noise quicker in first stage than one with 3180µS
pole
and
318µS zero (black curve).


Gain Stage Design
As an Initial observation, a higher gate bias in the second stage
forced by the gain of
the first stage would cause the first stage to bear a greater share of
the overall gain.
Figure 3: LSK170A SPICE
model for
reference 
.MODEL LSK170A NJF
+ BETA = 0.0378643
VTO = 0.4025156 LAMBDA
= 4.783719E3
+ IS =
3.55773E14
+ RD =
10.6565
RS =
6.8790487
+ CGD =
3.99E11
CGS =
4.06518E11
+ PB =
0.981382
FC =
0.5
+ KF =
0
AF
=
1

Stage One
I wanted
to choose source resistors small enough to make their noise
contribution insignificant compared to the JFET. This would lower
noise and allow the possiblity of noise improvement with better JFETs.
Resistor
noise
equation
(per
√Hz, figure of merit,
does not account for
bandwidth)

v_{nresistorrtHz} =
sqrt(4kTR)

Rearrange resistor noise equation to calculate equivalent input noise
resistance of JFET.
R =

v_{nresistorrtHz}^{2}
4kT

=

1nV^{2}
4 x 1.3806504e23 x 298.15ºK 
= 60.73254378Ω 
I would like to choose R
_{S} much lower than
60Ω to make their
contribution insignificant. However, I believe a 6Ω source
resistor would greatly raise distortion and bias for a small signal
transistor. Rather, instead I will match the source resistor to
the JFET noise resistance.
R_{2}R_{5} = 56Ω.
Some initial conditions would allow direct computation of bias, but
iteration (repetitive computer calculations) or a load line graph are
required to calculate the current bias to begin small signal analysis
from the
parameters given (V
_{gsdc} = 0V and R
_{s} = 56Ω).
Given k
_{n} (BETA) =
37.8643mA/V
^{2} and V
_{T} = 402.5156mV for LSK170A,
bias current
iterates to 2.551918mA.
Given LAMBDA = 4.783719m(V
^{1}) from LSK170A spice model
calculate r
_{ds}:
r_{ds} =

1
LAMBDA x i_{D0} 
=

1
4.783719m(V^{1}) x
2.551918mA 
= 81.9159kΩ 
Anticipating V
_{DS} biased at 4V maximum, add contribution of r
_{ds}
to effective I
_{D}:
I_{D} = 2.551918mA +

4V
81.9159kΩ 
=

2.60075mA

Calculate g
_{fs} and make a rough estimate of maximum possible
gain to continue calculations. (This is a situation where we need
to know the gain before we actually calculate it.)
g
_{fs} = 2 x sqrt(k
_{n}I
_{D}) = 2 x
sqrt(37.8643mA/V
^{2} x 2.60075mA) = 19.8470mS
A_{Vpreliminary} =

Apparent max load bias voltage
V_{GS}

=

V_{DD}  2V_{Tmax}
I_{D} x (R_{s}
+ 1/g_{fs}) 
=

48V  2(2V)
2.60075mA x (56Ω +
1/19.8470mS) 
= 159.0273565(V/V)

Want drain load much less
than r
_{ds}/4 to minimize affect of parameter variance on
equalization. Calculate bias limit on R
_{d}:
R_{d} <=

V_{DD}  (V_{G}+V_{Tmax})

(v_{gpeak} x A_{Vpreliminary})  (V_{DRAINSAFETYFACTOR})
I_{D} x 4

=

48V  (0V + 2V)  (14mV x
159.0273565)  4V
2.60075mA x 4 
= 3.82328kΩ 
Choose next lower 1% standard value: R
_{6} = 3.74kΩ
We must know Input bias to second stage to finish calculations for
first stage.
Make a more refined gain estimate for stage 1 to set stage 2 input bias:
A_{Vrefined} =

4 x R_{dtotal}
R_{s} + 1/g_{fs} 
=

4 x (R_{6}  (r_{ds}/4))
R_{s} + 1/g_{fs} 
=

4 x (3.74kΩ  20.479kΩ)
56Ω + 1/19.8470mS 
= 118.906(V/V)

Calculate peak signal to stage 2 from 14mV peak input:
v
_{gpeakstage2} = v
_{gpeakstage1} x 14mV = 118.906
x 14mV
_{peak} = 1.66468V
_{peak
}
A_{Vstage2} =

A_{Vtotal}
A_{Vstage1} 
=

2000
118.906 
= 16.82(V/V) 
V_{biasstage2} =

V_{DD}  V_{Tmax}

v_{gpeakstage2}  (V_{DRAINSAFETYFACTOR})
(A_{Vstage2} + 1)
+ A_{VSAFETYFACTOR} 
=

48V  2V
 1.66468V  4V
20 
= 2.01677V

Try round down to V
_{biasstage2} = 2V
Choose
R_{7} =
10MΩ,
calculate R
_{8}:
R_{8} = 10MΩ x

V_{biasstage2}
V_{DD}  V_{biasstage2}

= 10MΩ x

2V
48V  2V

= 434.783kΩ 
Choose next higher 1% standard value:
R_{8} = 442kΩ.
Calculate actual bias with standard values:
V_{biasstage2} =

48V x 442kΩ
10MΩ + 442kΩ 
= 2.03179V

Calculate final gain.
A_{Vstage1} =

4 x R_{dtotal}
R_{s} + 1/g_{fs} 
=

4 x (R_{6}  R_{7}
 R_{8}  (r_{ds}/4))
R_{s} + 1/g_{fs} 
=

4 x (3.74kΩ  10MΩ  442kΩ 
20.479kΩ)
56Ω + 1/19.8470mS 
= 118.024 = 41.4394dB

After stage 2 gain established,
I decide to recalculate R
_{6} for standard RIAA gain to get
less distortion. (Here  means subtract from parallel combination)
A_{Vstage1new} =

1000
A_{Vstage2} 
=

1000
13.3985 
= 74.6352(V/V)

R_{6} = 
A_{Vstage1}(R_{s}
+ 1/g_{fs})
4

 (R_{7}
 R_{8}  (r_{ds}/4)) = 
74.6352(56Ω +
1/19.8470mS)
4 
 (10MΩ  442kΩ 
20.479kΩ) = 
1.98502kΩ  19.5339kΩ 
R_{6} =

19.5339kΩ x 1.98502kΩ
19.5339kΩ  1.98502kΩ 
= 2.20955kΩ 
Would have chosen 2.2kΩ but for slight overgain. Round down to
nearest 1% value:
R_{6} =
2kΩ
Stage Two
Calculate r
_{ds}: from LAMBDA and desired 2mA bias
r_{ds} =

1
LAMBDA x i_{D0} 
=

1
4.783719m(V^{1}) x
2mA 
= 104.521kΩ 
Anticipating V
_{DS} biased at 4V maximum, add contribution of r
_{ds}
to effective I
_{D}:
I_{D} = 2mA +

4V
104.521kΩ 
=

2.03827mA

Add voltage element for R
_{s} to FET equation by Kirchoff's
voltage law and solve for R
_{s} given a desired 2mA bias.
V
_{G} = R
_{s}I
_{D} + V
_{T} +
sqrt(I
_{D}/k
_{n})
R
_{s}I
_{D} =
V
_{G}  V
_{T}
 sqrt(I
_{D}/k
_{n})
R_{s} =

V_{G}  V_{T}
 sqrt(I_{D}/k_{n})
I_{D} 
=

2.03179V  402.5156mV 
sqrt(2.03827mA/37.8643mA/V^{2})
2.03827mA 
= 1.08047kΩ 
Choose nearest 5% standard value:
R_{9} = 1.1kΩ.
This little round to standard value does not merit recalculation of I
_{D}.
Calculate bias limit on R
_{d:}
R_{d} <=

V_{DD}  V_{G} 
V_{Tmax}

v_{dpeak}  (V_{DRAINSAFETYFACTOR})
I_{D}

=

48V  2.03179V  2V  2.82843V 
4V
2.03827mA 
= 18.2212kΩ 
Calculate g
_{fs} and calculate gain.
g
_{fs} = 2 x sqrt(k
_{n}I
_{D}) = 2 x
sqrt(37.8643mA/V
^{2} x 2.03827mA) = 17.5702mS
Calculate R
_{d} for desired total gain of 66dB
A_{Vstage2target}
= 16.82(V/V) = 
R_{dtotal}
R_{s} + 1/g_{fs} 
=

R_{11}  r_{ds}
R_{s} + 1/g_{fs} 
R
_{dtotal} = A
_{Vstage2}(R
_{s} + 1/g
_{fs})
=
16.82(1.1kΩ
+
1/17.5702mS)
=
19.4593kΩ
Subtract r
_{ds} from parallel R
_{dtotal} combination:
R_{11} =

r_{ds} x R_{dtotal}
r_{ds}  R_{dtotal}

=

104.521kΩ x 19.4593kΩ
104.521kΩ  19.4593kΩ 
= 23.911kΩ 
This value for R
_{11} would violate the bias limit set before,
so R
_{11} defaults to bias limited value of 18.2212kΩ
Choose next lower 1% standard value:
R_{11} = 18.2kΩ
Calculate gain shortfall:
A_{Vstage2actual}
=

R_{dtotal}
R_{s} + 1/g_{fs}

=

R_{11}  r_{ds}
R_{s} + 1/g_{fs} 
=

18.2kΩ  104.521kΩ
(1.1kΩ + 1/17.5702mS) 
= 13.3985(V/V)

A
_{VLOSS} = 13.3985/16.82 = 796.582m
A
_{VLOSSdB} = 20log
_{10}(796.582m) = 1.97539dB
This is an acceptable design compromise.
SPICE shows distortion more than I would like.
Went back and recalculated R
_{6} of stage 1 for overall
RIAA standard 40dB of gain at 1kHz to lower distortion.
Calculate input capacitance to prepare to evaluate its affect on RIAA
network of previous stage (These formulas are those to calculate
reversebias diode capacitance which the gate forms with respect to
both the drain and the source.):
C_{GS} =

CGS
(1  V_{GS}/PB)^{0.5}

=

CGS
(1  (V_{T} + sqrt(I_{D}/k_{n}))/PB)^{0.5} 
C_{GS} =

4.06518e11
(1  (402.5156mV +
sqrt(2.03827mA/37.8643mA/V^{2}))/0.981382)^{0.5} 
= 37.5228pF

C_{GD} =

CGD
(1  V_{GD}/PB)^{0.5}

=

CGD
(1  (V_{G}  V_{DD})/PB)^{0.5} 
C_{GD} =

3.99e11
(1  (2.03179V(48V 
2.03827mA x 18.2kΩ))/0.981382)^{0.5} 
= 12.5923pF

A
_{V} at 2122Hz necessary to calculate Miller capacitance (C
_{M})
is
1/10
of
Stage
2
low
frequency
gain
of
13.3985
C_{G} = C_{GS} +
C_{M} = C_{GS} + C_{GD}(A_{V} + 1) =
37.5228pF + 12.5923pF(1.33985 + 1) = 66.9869pF 
Output Buffer
Figure 4: LSK170C SPICE
model for
reference. 
.MODEL LSK170C
NJF
+ BETA = 0.0278541
VTO = 0.800434
LAMBDA =
0.0122435
+ IS = 2.45217E14
+ RD =
12
RS
=
5.8
CGD
=
4.22E11
+ CGS =
4.23E11
PB = 0.9265487
+ FC =
0.5
KF
=
0
AF
=
1

R
_{12} limits shortcircuit current through Q
_{6} to
20mA
R
_{12} >= 48V/20mA = 2.4kΩ.
Choose 5% value:
R_{12} =
2.4kΩ.
Calculate
V
_{G} .
V
_{G} = V
_{DD}  i
_{DQ5}R
_{11}
= 48V
 2.03827mA x 18.2kΩ = 10.9035V
Min i
_{DSS} of 10mA sets I
_{D} limit. Choose half
at I
_{D} = 5mA.
Calculate r
_{ds}: from LAMBDA and desired 5mA bias
r_{ds} =

1
LAMBDA x i_{D0} 
=

1
0.0122435(V^{1}) x
5mA 
= 16.3352kΩ 
Given k
_{n} (BETA) = 27.8541mA/V
^{2} and V
_{T}
= 800.434mV for LSK170C, calculate R
_{s}:
R_{s} =

V_{G}  V_{T}
 sqrt(I_{D}/k_{n})
I_{D} 
=

10.9035V  800.434mV 
sqrt(5mA/0.0122435A/V^{2})
5mA 
= 2.21298kΩ 
Round up to next 5% value:
R_{13} =
2.4kΩ.
Output impedance of Q
_{6}
is the inverse of its operating ac transconductance g
_{fs}.
g
_{fs} = 2 x sqrt(k
_{n}I
_{D}) therefore
R_{outQ6} =

1
2 x sqrt(k_{n}I_{D}) 
=

1
2 x sqrt(27.8541mA/V^{2}
x 5mA) 
= 42.3682Ω 
This value will dominate the output impedance. Paralleling R
_{13}
and R
_{14} with it will only lower it slightly further.
Arbitrarily choose 5% value,
R_{14} =
100kΩ, only to ground output capacitor C
_{5}.
Calculate input capacitance to prepare to evaluate its affect on RIAA
network of previous stage:
C_{GS} =

CGS
(1  V_{GS}/PB)^{0.5}

=

CGS
(1  (V_{T} + sqrt(I_{D}/k_{n}))/PB)^{0.5} 
C_{GS} =

4.23e11
(1  (800.434mV +
sqrt(5mA/27.8541mA/V^{2}))/0.9265487)^{0.5} 
= 35.6658pF

C_{GD} =

CGD
(1  V_{GD}/PB)^{0.5}

=

CGD
(1  (V_{G}  V_{D})/PB)^{0.5} 
C_{GD} =

4.22e11
(1  (10.9035V  (48V 
(5mA
x 2.4kΩ)))/0.9265487)^{0.5} 
= 7.96283pF

Drain limiting resistor invokes Miller capacitance (C
_{M}) even
though it is not in the signal path. Calculate virtual gain with
respect to same and then calculate input capacitance:
A_{Vbuffer} =

R_{dtotal}
R_{s} + 1/g_{fs}

=

R_{12}  r_{ds}
R_{s} + R_{outQ6}

=

2.4kΩ  16.3352kΩ
2.4kΩ + 42.3682Ω 
= 856.774m(V/V)

C_{G} = C_{GS} +
C_{M} = C_{GS} + C_{GD}(A_{V} + 1) =
35.6658pF + 7.96283pF(856.773m + 1) = 50.451pF 
RIAA Analysis
Stage One
Calculate the effective network resistance and solve C
_{2} for
a pole of 75µS.
R
_{6network} = R
_{6}  R
_{7}
 R
_{8}  (r
_{ds}/4) = 2kΩ  10MΩ  442kΩ 
20.479kΩ = 1.81425kΩ
C_{2network} =

T_{pole}
R_{6network} 
=

75µS
1.81425kΩ 
= 41.3395nF 
Correct C
_{2} for input capacitance of next stage:
C_{2} = C_{2network}

C_{Gstage2} = 41.3395nF  66.9869pF = 41.2725nF 
Stage Two
Calculate the effective DC network resistance and solve for
R
_{11network} =
R
_{11}  r
_{ds} = 18.2kΩ  104.521kΩ = 15.5009kΩ
R
_{10} = R
_{11} / 9 = 15.5009kΩ / 9 = 1.72232kΩ
C_{4} =

T_{zero}
R_{10} 
=

318µS
1.72232kΩ 
= 184.635nF 
Input capacitance of next stage should not affect the 500.2Hz zero
formed by C
_{4} and R
_{10} but may affect the
50.02Hz pole in a small way only complicated calculations could
reveal.
These calculations would be like redoing those of
Calculating Passive RIAA
Equalization with input capacitance of the next stage in
place of
C2 of that circuit interacting with the network at a higher
frequency. I reserve this compensation for the SPICE analysis.
Adjustments
In spite of careful calculations, the RIAA network values will require
adjustments during SPICE evaluation due to unexpected and stray
effects. Even then, rounding to standard values will require
experimentation to get best frequency response curve. The parts list
will show these changes.
SPICE evaluation of unadjusted design circuit was immediately
excellent. The somewhat wavy gain plot sloped down from 20Hz to
20kHz by only 2.25dB.
Figure
5:
Frequency
response
of
unadjusted
design
circuit


SPICE Model, LSK170 SPICE
Subckt Models 
Optimizing RIAA network values in SPICE rids plot of waviness to slope
down from 20Hz to 20kHz by only 1.60dB. Calculations for
adjustments are made in the following linear manner. If
measurement increases with increase in component value, calculate
adjustment by:
value_{new} = 
value_{current} x

measurement_{target}
measurement_{observed}

Else if measurement decreases with increase in component value,
calculate adjustment by:
value_{new} = 
value_{current} x

measurement_{observed}
measurement_{target}

If relationship is strictly linear, you can meet your target with one
adjustment calculation. If not, repeatly recalculate and
resimulate
until the target is met or close enough for your tolerance
criteria. To help you bend your graph as you desire you should
note that frequency plot will slope down at a corresponding pole/zero
pair (one in the recorded preequalization and the other in the
equalization of your preamp) if any error is on the side of f
_{pole}<f
_{zero}
(T
_{pole}>T
_{zero}) and slope up if any error is on
the side of f
_{pole}>f
_{zero} (T
_{pole}<T
_{zero}).
You
can
make
your
sound
bright
or
warm
by
your adjustments.
Figure
5:
Frequency
response
of
SPICE
optimized
circuit 

SPICE Model, LSK170 SPICE
Subckt Models 
After careful rounding of component values plot slopes down from 20Hz
to 20kHz by only 1.30dB.
Figure
6:
Frequency
response
of
final
circuit
after
choosing
standard
component
values.


SPICE Model, LSK170 SPICE
Subckt Models 
Higher than anticipated JFET transconductance may require raising
supply voltage to prevent drain saturation. Unexpected distortion
of prototype may be aleviated by raising power supply voltage.
Other SPICE Findings
SNR = 102.98dB relative to 1V
_{rms} output. This would be
relative to a 10mV cartridge output amplified by 40dB gain at
1kHz. SNR
will vary
with cartridge output after you compensate with your volume control.
Fourier analysis for vout: (Distortion performance at 7.071mV
_{peak}(5mV
_{rms})
and
1kHz
and
breakdown
by
harmonic)
Fourier analysis for vout:
No. Harmonics: 10, THD: 0.0178052 %, Gridsize: 200, Interpolation
Degree: 1
Harmonic 
Frequency 
Magnitude 
Phase 
Norm. Mag 
Norm. Phase 
 
 
 
 
 
 
0 
0 
0 
0 
0 
0 
1 
1000 
0.879288 
92.635 
1 
0 
2 
2000 
0.000146834 
19.801 
0.000166992 
72.8345 
3 
3000 
5.41796e005 
38.326 
6.16175e005 
54.3094 
4 
4000 
3.23322e006 
95.464 
3.67709e006 
2.8289 
5 
5000 
1.56558e006 
131.85 
1.78051e006 
39.21 
6 
6000 
3.12765e007 
88.13 
3.55703e007 
4.50502 
7 
7000 
1.21373e006 
45.309 
1.38036e006 
47.3267 
8 
8000 
2.42554e007 
80.335 
2.75853e007 
12.3003 
9 
9000 
7.75152e007 
58.3996 
8.81568e007 
151.035 
Fourier analysis for vout: (Distortion performance at 100Hz and
proportionate level to 1kHz and
breakdown by harmonic)
No. Harmonics: 10, THD: 0.0190292 %, Gridsize: 200,
Interpolation Degree: 1
Harmonic 
Frequency 
Magnitude 
Phase 
Norm. Mag 
Norm. Phase 
 
 
 
 
 
 
0 
0 
0 
0 
0 
0 
1 
100 
0.891848 
90.243 
1 
0 
2 
200 
0.000169612 
170.701 
0.00019018 
260.944 
3 
300 
5.79251e006 
75.974 
6.49495e006 
14.2693 
4 
400 
3.3312e007 
49.7897 
3.73516e007 
140.033 
5 
500 
2.1084e007 
94.8152 
2.36408e007 
185.058 
6 
600 
1.69153e007 
96.0689 
1.89666e007 
186.312 
7 
700 
1.44333e007 
96.9693 
1.61835e007 
187.212 
8 
800 
1.2705e007 
97.6061 
1.42457e007 
187.849 
9 
900 
1.13432e007 
98.8471 
1.27188e007 
189.09 
Fourier analysis for vout: (Distortion performance at 10kHz and
proportionate level to 1kHz and
breakdown by harmonic)
No. Harmonics: 10, THD: 0.345553 %, Gridsize: 200, Interpolation
Degree: 1
Harmonic 
Frequency 
Magnitude 
Phase 
Norm.Mag 
Norm.Phase 
 
 
 
 
 
 
0 
0 
0 
0 
0 
0 
1 
10000 
0.821345 
102.31 
1 
0 
2 
20000 
0.00283777 
107.17 
0.00345502 
4.8656 
3 
30000 
4.86413e005 
79.038 
5.92215e005 
23.2697 
4 
40000 
2.79079e006 
168.487 
3.39783e006 
270.794 
5 
50000 
9.02139e007 
74.142 
1.09837e006 
28.1659 
6 
60000 
9.62636e007 
84.247 
1.17202e006 
18.0606 
7 
70000 
8.13981e007 
83.821 
9.91034e007 
18.4866 
8 
80000 
7.11331e007 
82.815 
8.66056e007 
19.4925 
9 
90000 
6.33031e007 
81.892 
7.70725e007 
20.4162 
Miscellaneous Calculations
Now set coupling capacitor values C
_{3} and C
_{5} for
best bass response:
Initially desire both highpass poles at 0.1Hz for nearly no affect at
20Hz.
R
_{pole} = R
_{6}  (r
_{ds}/4) + R
_{7}
 R
_{8 }= 2kΩ  20.479kΩ + 10MΩ  442kΩ = 1.82206kΩ +
423.291kΩ = 425.113kΩ
C_{3} =

1
2πf_{pole}R_{pole} 
=

1
2π x 0.1Hz x 425.113kΩ 
= 3.74383µF

Round up to next 20% standard value. Choose
C_{3} = 3.9µF
polyethylene.
Assuming a high impedance load (R
_{L }>= 10kΩ):
R
_{pole} = R
_{outQ6} + R
_{14}
 R
_{L }= 42.3682Ω + 100kΩ  10kΩ = 9.13328kΩ
C_{5} =

1
2πf_{pole}R_{pole} 
=

1
2π x 0.1Hz x 9.13328kΩ 
= 174.258µF

Round up to next 10% standard value. Choose
C_{5} = 180µF
electrolytic
If you want a polyethylene capacitor here choose C
_{5} = 10µF
and recalculate pole:
f_{pole} =

1
2πC_{5}R_{pole} 
=

1
2π x 10µF x 9.13328kΩ 
= 1.74258Hz

Highpass response is only down 0.033dB at 20Hz with this choice of
0.1Hz and
1.74258Hz poles.
You may recalculate C
_{5} if you want to drive 600Ω.
Calculate load current from power supplies V
_{DD1, }V
_{DD2,
}and V
_{DD3}.
i
_{DD1} = i
_{Q1BIAS} x 4 + i
_{R7R8} =
2.551918mA x 4 + 48V/(10MΩ + 442kΩ) = 10.2123mA
i
_{DD2} = i
_{Q6BIAS} = 2.03827mA
i
_{DD3} = i
_{Q6BIAS} = 5mA
Design Decisions Left to You
 R_{1} and C_{1} should be calculated per article Phono
Termination Calculations and
Calculator.
 This circuit and its analysis is only given as a design example;
change
everything if you like.
 A low noise 48V power supply. The Line Level Class A Power Supply
presented earlier will require a design improvement to deliver
48V. The LM317 used as a preregulator has a 40V limit on the
input/output differential. See the LM317 datasheet for ideas.
 Whether protection zeners (39V) should be used to protect from
drain overvoltage. (Connected from drain to source or
ground.) Load resistors may provide sufficient protection.
 Resistor wattage given for normal operation. Decide whether
more wattage is needed at power up.
 In spite of careful design, transistor parameter variations may
require more adjustments during the prototyping process. The
specifications in this design are only valid if the JFETs match the
SPICE model parameters. ;=(
Document History
June 26, 2010 Created
July 3, 2010 Recalculated with 48V power supply and RIAA standard
gain.
January 26, 2011 Removed personal comment at
beginning. Made minor symbol improvements.
March 26, 2011 Corrected numerical typo at end of first stage
calculations not affecting their results and a misspelling in the SPICE
results.