Copyright © 2010
Created January 2, 2010
Updated January 27, 2010. See document history at end for details.
Active Inductor Example
JFET Phono Preamp
This is an example only. It is not intended to be final or
complete design.
Figure
1: Schematic


Parts List


Q_{1}Q_{4} 
2N3918 nch jfet 
Q_{5},Q_{6} 
BS170 nch mosfet 
R_{1},R_{3},R_{5},R_{7}

220Ω, 5% 
R_{2},R_{4},R_{6},R_{8}

220Ω, 5% 
R_{2L}

165kΩ, 1% 
R_{2N}

23.7kΩ, 1%

C_{1N,a}

13nF, 1% or 5% 
C_{1N,b}

240pF, 1% or 5% 
C_{2N,a} 
4.3nF, 1% or 5% 

C_{2N,b}

240pF, 1% or 5% 
R_{1L} 
105kΩ, 1%

C_{L} 
10,000µF, 25V
electrolytic

R_{9},R_{11}

1kΩ, 5%

R_{12}

82Ω, 5%

R_{13}

1kΩ, 5%

C_{2}

100µF, 25V
electrolytic

R_{15}

1kΩ pot 
S_{1},S_{2} 
SPST reed relay,
normally closed, coil rated 10mA@5V




Remaining values are left for you to calculate. See text.

Initial Design Decisions
 Discrete voltage input design with 46db gain at 1kHz will amplify
5mV rms input to produce 1V rms
before attenuator.
 Q_{1}Q_{4} are 2N3918 nch jfet (6nV/rtHz noise
is
not
bad, you may choose a better device)
 I chose four devices because multiple parallel devices increase
S/N by sqrt(# of devices). In this case the effective
noise specification is bettered to 3nV/rtHz.
 Q_{5},Q_{6} are BS170 nch mosfet (commonly
available)
 v_{gs,max} of Q_{6}
of 20V limits V_{DD} due to
startup relays. Choose V_{DD} = 18V.
 Let bias of active inductor set bias to gate of Q6 to eliminate
coupling capacitor.
v_{g,Q5}
= 
(V_{DD}v_{gsQ5max})+v_{sgQ1max}
2

=

18V2V+8V
2

= 12V

 R_{2L} of active inductor functions as R_{1} of
passive
RIAA network.
 I chose to do the small signal classa design with a fourier
series
based distortion predictor tool out of convenience. Small signal
classa design is not in the scope of this article.
 Because of possibility of negative feedback from buffer stage
back to gain stage through power supply, I decided to recommend two
power supply taps.
Gain Stage Design
Although I used a convenient fourier series analysis tool to do the
small signal analysis, there were some design decisions. I wanted
to choose gate and source resistors small enough to make their noise
contribution insignificant compared to the JFET. This would lower
noise and allow the possiblity of noise improvement with better JFETs.
Resistor
noise equation (per rtHz, figure of merit, does not account for
bandwidth)

v_{nresistorrtHz} =
sqrt(4kTR)

Rearrange resistor noise equation to calculate equivalent input noise
resistance of JFET.
R =

v_{nresistorrtHz}^{2}
4kT

=

6nV^{2}
4 x 1.3806504e23 x 298.15ºK 
= 2.186371576kΩ 
I choose R
_{G} and R
_{S} 10 times lower to make their
noise contribution insignificant.
R1R8 = 220Ω.
Because the fourier series analysis resulting from this choice was
excellent, I made no further adjustments to these values.
Fourier Series Analysis of Q_{1}Q_{4} (excluding
drain load)
Analysis of Common Source Circuit
transistor type = JFET
transconductance = 5.5mS
threshold voltage = 3V
source resistor = 220Ω
Input signal (peak) = 7.0710678mV
Input bias = 0V
Output signal (peak) = 21.585572µA
Output bias = 7.8662828mA
^{1}
Gain = 3.0526609mS
Total distortion = 1.6210607nA = 0.00750993% = 82.4873dB
Breakdown by harmonic
harmonic 
value 
percent 
dB 

0 
7.8662844mA^{1} 
36442.32534044% 
51.23dB 
DC Offset

1 
21.585572µA 
100.00000000% 
0.00dB 
Fundamental 
2 
1.6210607nA 
0.00750993% 
82.49dB 

RIAA Analysis
Refer
Calculating Passive RIAA
Equalization in article Phono Equalization
Calculations.
From this fourier analysis we can calculate R
_{1} of Passive
RIAA network (aka R
_{2L})
R_{2L} =

(Low frequency RIAA boost
relative to 1kHz) x (1kHz output voltage)
(Output signal current) x
(#parallel devices) 
=

10 x 1.414213562V
21.585572µA x 4 
= 163.791532kΩ 
Round to nearest 1% value.
R_{2L} =
165kΩ
Given R
_{1}:R
_{2}
= 6.877358491
R_{2N} = 
165kΩ
6.877358491 
= 23.99176955kΩ 
Round to nearest 1% value.
R_{2N} =
23.7kΩ
Given R
_{1}C
_{1} = 2187µS
C_{1N} =

2187µS
165kΩ 
= 13.25454545nF

Round down to nearest 5% value: 13nF
Choose parallel 5% value to makeup remainder: 240pF
C_{1N} = 13nF + 240pF
Given R
_{1}C
_{2} = 750µS
C_{2N} =

750µS
165kΩ 
= 4.545454545nF

Round down to nearest 5% value: 4.3nF
Choose parallel 5% value to makeup remainder: 240pF
C_{2N} = 4.3nF + 240pF
Active Inductor Analysis
Refer article
Active Inductor Load.
 Choose R_{2L} for gain of overall circuit.
R
_{2L} chosen already in RIAA analysis.
BS170 specification: g
_{m}
= 320mS.
g
_{fs} = 2 x sqrt(g
_{m}i
_{D})
= 2 x sqrt(320mS x 7.8662828mA x 4) = 200.6872391mS
R_{1L} =

R_{2L}

Vbias
v_{T}+sqrt(i_{D}/g_{m}) 
1



=

165kΩ

6V
2V+sqrt((7.8662828mA
x 4)/320mS) 
1



= 103.5527796kΩ 
Round to nearest 1% value:
R_{1L} =
105kΩ
 Choose C_{L} to set the pole frequency the desired amount
below the
passband. (equation (21))
C_{L} =

g_{fs}R_{1L}+1
2πf_{POLE}R_{1L} 
=

(200.6872391mS x 105kΩ)+1
2π x 5Hz x 105kΩ 
= 6.388376376mF

6800µF would work here. I would rather choose a larger common
value (
C_{L} =
10,000µF) and solve for a lower pole.
f_{POLE} =

g_{fs}R_{1L}+1
2πC_{L}R_{1L} 
=

(200.6872391mS x 105kΩ)+1
2π x 10mF x 105kΩ 
= 3.194188188Hz 
 Determine if a bypass switch is needed to charge the capacitor on
startup.
Power on relay added at beginning of design.
Calculate charge time for C
_{L}:
Rearrange capacitor equation above and calculate time. (2V
presumes v
_{gs} not much more than v
_{T})
Δt =

CΔv
i_{D} 
=

10mF x 2V
7.8662828mA
x 4 
= 635.6242366mSec

Q_{6} Circuit Design
My design goal here was reasonably low output impedance. 1kΩ
output impedance would have been low enough to minimize voltage loss
into a typical 47kΩ load. I choose 500Ω instead on the far chance
of driving a 600Ω load with a tolerable voltage loss.
Fourier Series Analysis of Q_{6} Circuit
Note: This analysis based on a more convenient equivalent model
of source circuit. Two 500Ω are modeled in series with one
bypassed by a capacitor in place of the parallel circuit shown.
Analysis of Common Source Circuit
transistor type = MOSFET
transconductance = 320mS
threshold voltage = 2V
source resistor = 500Ω
Input signal (peak) = 1.4142136V
Input bias = 7V
Output signal (peak) = 2.7910912mA
Output bias = 9.8041739mA
^{1}
Gain = 1.9735995mS
Total distortion = 950.79116nA = 0.03406521% = 69.3538dB
Breakdown by harmonic
harmonic 
value 
percent 
dB 

0 
9.805058mA^{1} 
351.29836800% 
10.91dB 
DC Offset

1 
2.7910912mA 
100.00000000% 
0.00dB 
Fundamental 
2 
888.84698nA 
0.03184586% 
69.94dB 

3 
56.727241nA 
0.00203244% 
93.84dB 

4 
4.7600566nA 
0.00017054% 
115.36dB 

5 
456.88194pA 
0.00001637% 
135.72dB 

Miscellaneous Calculations
R
_{12} limits charge current through Q
_{6} to C
_{2}
to <500mA
R
_{12} >= 20V/500mA = 40Ω
Choose
R_{12} =
82Ω.
Want to set C
_{2} for as low a highpass pole as C
_{L}.
First find R
_{equiv} of pole. Output impedance of Q
_{6}
is the inverse of its operating ac transconductance g
_{fs}.
g
_{fs} = 2 x sqrt(g
_{m}i
_{D}) therefore
R_{outQ6} =

1
2 x sqrt(g_{m}i_{D}) 
=

1
2 x sqrt(320mS x
9.8041739mA) 
= 8.92667066Ω 
R_{equiv} = (R_{outQ6
} R_{13}) + R_{15} = 
R_{outQ6 }x R_{13}
R_{outQ6 }+ R_{13} 
+ R_{15} = 1.00884769kΩ 
C_{2} =

1
2πf_{pole}R_{equiv} 
=

1
2π x 2.348779238Hz x
1.00884769kΩ 
= 67.16643973µF

Choose
C_{2} =
100µF.
Choose R
_{10} and R
_{14} to set 10mA through
relay coil.
R_{10} =

V_{DD}v_{COIL}
i_{COIL}

=

18V5V
10mA 
= 1.3kΩ 
Calculate load current from power supplies V
_{DD1 }and V
_{DD2}.
i
_{DD1} = i
_{Q1BIAS} x 4 + i
_{RELAYCOIL} =
7.8662828mA x 4 + 10mA = 41.4651312mA
i
_{DD2} = i
_{Q6BIAS} + i
_{RELAYCOIL = }
9.8041739mA + 10mA = 19.8041739mA
Design Decisions Left to You
 Ri and Ci should be calculated per article Phono
Termination Calculations and
Calculator.
 Gate resistors were somewhat arbitrarily chosen. They seem
to be good values. I know that the 1kΩ values work with the
BS170. I have seen many jfet schematics without gate resistors at
all. Increase them if any oscillations occur.
 Relay components C_{1}
and C_{3} must be calculated as follows:
C
_{1} must be chosen by calculation or experimentation to
exceed C
_{L}
charge time calculated above (432.2244809mSec). C
_{3}
would then be
chosen for a somewhat longer delay to prevent a pop from the activation
of the other relay.
 This circuit and its analysis is only given as an example; change
everything if you like.
 A low noise 18V power supply. I recommend the circuit of
article Line Level Class A Power Supply.
^{1}There is a seeming discrepancy
in the fourier
analysis between the cited output bias and the same value given in the
analysis. The first value is the bias without any signal and the
second with a signal. This effect is created by the same asymetrical
transfer curve that gives us a desireable second order distortion
characteristic. The positive half of the signal is amplified more
than the negative half. As a result the dc bias is modulated by
the average signal level. This small component amounts to AM
demodulation of the music signal. Abstractly, I had already
anticipated this effect. I would be curious what effect this has
on the overall sound. Is is detrimental, or does it add an extra
euphonic bass urge?
Document History
January 2, 2010 Created
January 2, 2010 Minor Updates.
January 5, 2010 Recommend split power supply to prevent
feedback.
Update schematic to show change. Recommend specific power supply.
January 5, 2010 Choose relays S1 and S2, calculate their series
resistors, and calculate specific load current for each power supply
tap.
January 9, 2010 Added footnote explaining how fourier series
analysis
shows modulation of dc bias by music signal.
January 17, 2010 Added design criteria for classa biasing
decisions. Recalculate Active Inductor Analysis due to
miscalculation of g_{fs}.
January 23, 2010 Correct schematic in vicinity of Q_{4},
R_{7}, and R_{2N}.
January 27, 2010 Minor improvement to writing style.