* Verify current-input riaa design equations * compensation zero in first stage * SPICE version: Spice Opus 2.31 v1 vsigin 0 dc 0 ac 1 sin 0 707.107mV 1kHz xinvriaa vsigin vsigin2 0 invriaa xcartload vsigin2 vin cartload * first stage with 3180us pole and compensation zero eu1 vis 0 0 vin 1E6 r2 vin r1r2 14.6113k r1 r1r2 vis 100k c1 r1r2 vis 31.8n * second stage with 318us zero and 75us pole eu2 vout 0 0 vnu2 1E6 r3 vis r3r4 2.4k c2 vis r3r4 132.5n r4 r3r4 vnu2 740.741 r5 vnu2 vout 32.4k * rl vout 0 47k * .subckt cartload vin vout l vin vl2rs 300m rs vl2rs vout 740 *ctotal vout 0 251p rl vout 0 47k .ends .include ./invriaa2.txt .end .control ac dec 25 10 100k setplot ac1 plot vdb(vout) .endc