* Verify current-input riaa design equations * compensation zero in second stage * SPICE version: Spice Opus 2.31 v1 vsigin 0 dc 0 ac 1 sin 0 707.107mV 1kHz xinvriaa vsigin vsigin2 0 invriaa xcartload vsigin2 vin cartload * first stage with 3180us pole and 318us zero eu1 vis 0 0 vin 1E6 r2 vin r1r2 10k r1 r1r2 vis 90.9k c1 r1r2 vis 34.9835n * second stage with compensation zero and 75us pole eu2 vout 0 0 vnu2 1E6 r3 vis r3c2 1k c2 r3c2 vnu2 75n r4 vis vnu2 4.42k r5 vnu2 vout 44.2k * rl vout 0 47k * .subckt cartload vin vout l vin vl2rs 300m rs vl2rs vout 740 ctotal vout 0 251p rl vout 0 47k .ends .include ./invriaa2.txt .end .control ac dec 25 10 100k setplot ac1 plot vdb(vout) .endc