two gain stage jfet preamp, 60db gain, design values
vsupplypos1 vdd1 0 dc 48V
vsupplypos2 vdd2 0 dc 48V
vsupplypos3 vdd3 0 dc 48V
* v1 vin 0 dc 0 ac 1 sin 0 7.071mV 1kHz
v1 vsigin 0 dc 0 ac 1 sin 0 1.414213562V 1kHz
x1 vsigin vin 0 invriaa
* v2 vin 0 dc 0 ac 1 distof1 0.005v 0
* stage 1
* r1 vin 0 47k
* c1 vin 0 100p
j1 vstage1 vin j1s lsk170a
r2 j1s 0 56
j2 vstage1 vin j2s lsk170a
r3 j2s 0 56
j3 vstage1 vin j3s lsk170a
r4 j3s 0 56
j4 vstage1 vin j4s lsk170a
r5 j4s 0 56
* r1n calculated 
r6 vdd1 vstage1 2k
* c2
c2 vdd1 vstage1 41.2725n
c3 vstage1 vstage1ac 3.9u
* stage 2, set bias 5V
r7 vdd1 vstage1ac 10meg
r8 vstage1ac 0 442k
j5 vstage2 vstage1ac j5s lsk170a
r9 j5s 0 1.1k
r11 vdd2 c1tor2 18.2k
r10 c1tor2 vstage2 1.72232k
* c4
c4 vdd2 c1tor2 184.635n
* buffer
j6 j6d vstage2 j6s lsk170c
r12 vdd3 j6d 2.4k
r13 j6s 0 2.4k
c5 j6s vout 180u
r14 vout 0 100k
.include ./invriaa2.txt
.include ./lsk170.txt
.end
.control
* dc v1 0 0 0
* setplot dc1
* print vstage2
noise v(j6s) v1 lin 19980 20Hz 20kHz
setplot noise2
print vdb(onoise_total)/2
ac dec 25 10Hz 100kHz
setplot ac1
plot vdb(j6s)
* pz vstage1ac 0 vstage2 0 vol pz
* setplot pz1
* print -1/pole
* print -1/zero[4]
* disto dec 1 100hz 100hz
* setplot disto1
* print mag(vout)*100
* setplot disto2
* print mag(vout)*100
* tran 10us 202ms 200ms
.endc